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? semiconductor components industries, llc, 2014 may, 2014 ? rev. 2 1 publication order number: ncp1126/d ncp1124, ncp1126, NCP1129 high voltage switcher for offline power supplies the ncp112x products integrates a fixed?frequency peak current mode controller with a low on?resistance, 650 v mosfet. available in a pdip?7 package, the ncp112x offers a high level of integration, including soft?start, frequency?jittering, short?circuit protection, thermal shutdown protection, frequency foldback mode and skip?cycle to reduce power consumption in light load condition, peak current mode control with adjustable internal ramp compensation and adjustable peak current set point. during nominal load operation, the part switches at one of the available frequencies (65 or 100 khz). when the output power demand diminishes, the ic automatically enters frequency foldback mode and provides excellent efficiency at light loads. when the power demand reduces further, it enters into a skip mode to reduce the standby consumption down to no load condition. protection features include: a timer to detect an overload or a short?circuit event with auto?recovery or latch protection, and a built?in v cc overvoltage protection. the switcher also provides a jittered 65 khz or 100 khz switching frequency to improve the emi. features ? built?in 650 v, 1 a mosfet with r ds(on) of 8.6 for ncp1124 ? built?in 650 v, 1.8 a mosfet with r ds(on) of 5.4 for ncp1126 ? built?in 650 v, 5.5 a mosfet with r ds(on) of 2.1 for NCP1129 ? fixed?frequency 65 or 100 khz current mode control with adjustable internal ramp compensation ? adjustable current limit with external resistor ? frequency foldback down to 26 khz and skip?cycle for light load efficiency ? frequency jittering for emi improvement ? less than 100 mw standby power @ high line ? eps 2.0 compliant ? 7?pin package provides creepage distance ? these are pb?free devices table 1. output power table (note 1) product 230 vac 15% (note 4) 85 ? 265 vac adapter (note 2) peak or open frame (note 3) adapter (note 2) peak or open frame (note 3) ncp1124 12 w 27 w 6 w 14 w ncp1126 15 w 32 w 10 w 17 w NCP1129 28 w 43 w 20 w 26.5 w 1. 12 v output voltage with 135 v reflected output voltage 2. typical continuous power in a non-ventilated enclosed adaptor measured at 50 c ambient temperature. 3. maximum practical continuous power in an open-frame design at 50 c ambient temperature 4. 230 v ac or 115 v ac with voltage doubler. pdip?7 p suffix case 626b marking diagrams http://onsemi.com see detailed ordering and shipping information on page 17 o f this data sheet. ordering information 112xypzzz awl yywwg 1 x = specific device code 4 = ncp1124 6 = ncp1126 9 = NCP1129 y = a or b a = latch b = auto?recovery zzz = frequency 65 = 65 khz 100 = 100 khz a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package
ncp1124, ncp1126, NCP1129 http://onsemi.com 2 figure 1. typical application table 2. pin function description pin no. pin name pin description 1 vcc this pin is connected to an external auxiliary voltage and supplies the controller. when above a certain level, the part fully latches off. 2 fb feedback input. hooking an optocoupler collector to this pin will allow regulation. 3 cs this pin monitors the primary peak current but also offers a means to introduce ramp compensation. 4 source source of the internal mosfet. this pin is typically connected to the source of a grounded sense resistor. 5 drain the drain of the internal mosfet. these pins connect to the transformer terminal and can withstand up to 650 v. 6 drain 7 ? removed for creepage distance. 8 gnd ground reference. table 3. options switcher package frequency short?circuit protection ncp1124ap65g pdip?7 65 khz latch ncp1124bp65g pdip?7 65 khz auto?recovery ncp1124ap100g pdip?7 100 khz latch ncp1124bp100g pdip?7 100 khz auto?recovery ncp1126ap65g pdip?7 65 khz latch ncp1126bp65g pdip?7 65 khz auto?recovery ncp1126ap100g pdip?7 100 khz latch ncp1126bp100g pdip?7 100 khz auto?recovery NCP1129ap65g pdip?7 65 khz latch NCP1129bp65g pdip?7 65 khz auto?recovery NCP1129ap100g pdip?7 100 khz latch NCP1129bp100g pdip?7 100 khz auto?recovery
ncp1124, ncp1126, NCP1129 http://onsemi.com 3 figure 2. functional block diagram v cc and logic management double hiccup + ? clamp r s q q power on reset 65/100 khz clock + ? frequency foldback + ? leb r s q q vcc drain source power on reset + gnd cs fb vdd 4 ms 5 s + ? frequency modulation slope compensation 250 mv peak current freeze the soft start is activated ? startup process ? auto recovery r fb /4 v skip r ramp v fold v dd v ilim i pflag 4 k v ovp r lim u vlo i pflag v dd ? + + ? + ?
ncp1124, ncp1126, NCP1129 http://onsemi.com 4 table 4. maximum ratings (note 5) rating symbol value unit drain input voltage (referenced to source terminal) ncp112x v drain ?0.3 to 650 v drain maximum pulsed current NCP1129 (10 s single pulse, t j = 25 c) ncp1126 ncp1124 i dm 27 11 7 a single pulse avalanche energy ncp1126, NCP1129 ncp1124 e as 96 60 mj supply input voltage v cc(max) ?0.3 to 35 v current sense input voltage v cs ?0.3 to 10 v feedback input voltage v fb ?0.3 to 10 v operating junction temperature t j ?40 to 150 c storage temperature range t stg ?60 to 150 c power dissipation (t a = 25 c, 2 oz cu, 600 mm 2 printed circuit copper clad) p d 1.5 w thermal resistance, junction to ambient 2 oz cu printed circuit copper clad low conductivity (note 6) high conductivity (note 7) r ja 128 78 c/w esd capability (note 8) human body model esd capability per jedec jesd22?a114f. machine model esd capability per jedec jesd22?a115c. charged?device model esd capability per jedec jesd22?c101e. 2000 200 500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 5. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78. 6. low conductivity board. as mounted on 40 x 40 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper trances and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection of zero ai r flow. 7. high conductivity board. as mounted on 40 x 40 x 1.5 mm fr4 substrate with a single layer of 600 mm 2 of 2 oz copper trances and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection of zero a ir flow. 8. the drain pins (5 and 6), are rated to the maximum voltage of the device, or 650 v.
ncp1124, ncp1126, NCP1129 http://onsemi.com 5 table 5. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values, t j is ?40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage operating hysteresis v cc increasing v cc decreasing v cc(on) ? v cc(off) v cc(on) v cc(off) v cc(hys) 15.75 7.75 6.0 17 8.5 ? 20 9.25 ? v v cc overvoltage protection threshold v cc(ovp) 26.3 28 29.3 v v cc overvoltage protection filter delay t ovp(delay) ? 26 ? s v cc clamp voltage in latch mode i cc = 500 a v zener 5 6.2 7.15 v supply current startup current skip current operating current at 65 khz operating current at 100 khz v cc = v cc(on) ? 0.5 v v fb = v skip ? 0.1 v i fb = 50 a, f sw = 65 khz i fb = 50 a, f sw = 100 khz i cc1 i cc2 i cc3 i cc4 ? ? ? ? ? 700 1900 3300 15 900 3100 4000 a current consumption in latch mode t j = ?40 c to 125 c i cc(latch) 42 ? ? a power switch circuit off?state leakage current t j = 125 c, v drain = 650 v i drain(off) ? ? 20 a breakdown voltage t j = 25 c, i drain = 250 a, v fb = 0 v v br(dss) 650 ? ? v on state resistance NCP1129 ncp1126 ncp1124 i drain = 100 ma v cc = 10 v, t j = 25 c v cc = 10 v, t j = 125 c v cc = 10 v, t j = 25 c v cc = 10 v, t j = 125 c v cc = 10 v, t j = 25 c v cc = 10 v, t j = 125 c r ds(on) ? ? ? ? ? ? 2.1 ? 5.4 ? 8.6 ? 2.75 5.0 7.7 13.1 9.5 20.3 output capacitance NCP1129 ncp1126 ncp1124 v ds = 25 v, v cc = 0 v, f = 1 mhz v ds = 25 v, v cc = 0 v, f = 1 mhz v ds = 25 v, v cc = 0 v, f = 1 mhz c oss ? ? ? 67.3 29.2 16.5 ? ? ? pf switching characteristics ncp1124 rise time fall time ncp1126 rise time fall time NCP1129 rise time fall time (v ds = 325 v, i drain = 1 a , v gs = 10 v, r g = 4.7 ) (v ds = 325 v, i drain = 1.8 a , v gs = 10 v, r g = 4.7 ) (v ds = 325 v, i drain = 5.5 a , v gs = 10 v, r g = 4.7 ) t r t f t r t f t r t f ? ? ? ? ? ? 4.25 9.32 7.44 5.94 7.54 5.94 ? ? ? ? ? ? ns current sense current sense voltage threshold v cs increasing, t j = 25 c v cs increasing v ilim1 v ilim2 730 720 785 800 840 880 mv cycle by cycle current sense propagation delay NCP1129 ncp1126 ncp1124 v cs dv/dt = 1 v/ s, measured from v ilim1 to drv falling edge t cs( delay) ? ? ? 100 50 50 150 150 150 ns cycle by cycle leading edge blanking duration t cs(leb) ? 320 400 ns internal oscillator oscillation frequency 65 khz version 100 khz version f osc1 f osc2 61 92 65 100 71 108 khz maximum duty ratio d max 78 80 82 % frequency jittering in percentage of f osc f jitter ? 5 ? %
ncp1124, ncp1126, NCP1129 http://onsemi.com 6 table 5. electrical characteristics (v cc = 12 v, for typical values t j = 25 c, for min/max values, t j is ?40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions feedback section internal pull?up resistor r up ? 13 ? k equivalent ac resistor from fb to gnd r eq ? 15 ? k v fb to internal current setpoint division ratio i ratio ? 4 ? ? feedback voltage below which the peak current is frozen v fb(freeze) 0.85 1 1.15 v frequency foldback frequency foldback level on the fb 47% of maximum peak current v fb(fold) 1.35 1.5 1.78 v transition frequency below which skip?cycle occurs f trans 22 26 30 khz feedback voltage level when frequency foldback ends f sw = f min v fb(fold,end) 410 450 490 mv skip?cycle level voltage on the fb pin v skip 360 400 440 mv hysteresis on the skip comparator v skip(hys) ? 40 ? mv fault protection soft?start period measured from 1 st drive pulse to v cs = v ilim t sstart ? 4.0 ? ms overload fault timer v cs = v ilim t ovld 35 50 65 ms temperature management temperature shutdown (note 9) tsd 130 ? ? c hysteresis guaranteed by design ? 20 ? c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 9. the value is not subjected to production test ? verified by design/characterization. the thermal shutdown temperature refers to the junction temperature of the controller.
ncp1124, ncp1126, NCP1129 http://onsemi.com 7 typical characteristics figure 3. ncp1124 i cc2 vs. junction temperature temperature ( c) i cc2 ( a) 65 khz 100 khz 725 720 715 710 705 700 695 690 685 ?50 ?25 0 25 125 100 50 75 ?50 ?25 0 25 125 100 50 75 figure 4. ncp1124 i cc3 vs. junction temperature temperature ( c) 2.2 i cc3 (ma) 65 khz 100 khz 2.15 2.1 2.05 2 1.95 1.9 65 khz 100 khz figure 5. ncp1126 i cc2 vs. junction temperature temperature ( c) 125 85 25 0 ?40 660 670 680 690 700 710 720 730 i cc2 ( a) 65 khz 100 khz figure 6. ncp1126 i cc3 vs. junction temperature temperature ( c) 125 85 25 0 ?40 2.0 2.1 2.2 2.3 2.4 2.5 2.6 i cc3 (ma) 65 khz 100 khz figure 7. NCP1129 i cc2 vs. junction temperature temperature ( c) figure 8. NCP1129 i cc3 vs. junction temperature temperature ( c) 125 100 85 25 0 ?25 ?40 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i cc3 (ma) 125 85 25 0 ?40 690 695 700 705 710 715 720 725 i cc2 ( a) 65 khz 100 khz 65 khz 100 khz ?25 100
ncp1124, ncp1126, NCP1129 http://onsemi.com 8 typical characteristics figure 9. ncp1124 i cc(latch) vs. junction temperature temperature ( c) ?50 0 10 20 30 40 i cc(latch) ( a) 125 100 ?25 0 25 50 75 figure 10. ncp1124 v ilim vs. junction temperature temperature ( c) v ilim (v) ?50 125 100 ?25 0 25 50 75 65 khz 100 khz 65 khz 100 khz 0.760 0.765 0.770 0.775 0.780 0.785 0.790 0.795 figure 11. ncp1126 i cc(latch) vs. junction temperature temperature ( c) 125 85 25 0 ?40 0 10 20 30 40 i cc(latch) ( a) 65 khz 100 khz figure 12. ncp1126 v ilim vs. junction temperature temperature ( c) 125 85 25 0 ?40 0.760 0.765 0.770 0.775 0.780 0.785 0.790 0.795 v ilim (v) 65 khz 100 khz figure 13. NCP1129 i cc(latch) vs. junction temperature temperature ( c) 125 100 85 25 0 ?25 ?40 15 20 25 30 35 40 i cc(latch) ( a) 65 khz 100 khz figure 14. NCP1129 v ilim vs. junction temperature temperature ( c) 125 100 85 25 0 ?25 ?40 0.770 0.775 0.780 0.785 0.790 0.795 v ilim (v) 65 khz 100 khz
ncp1124, ncp1126, NCP1129 http://onsemi.com 9 typical characteristics figure 15. ncp1124 v freeze vs. junction temperature temperature ( c) v freeze (v) ?50 1.035 125 100 ?25 0 25 50 75 1.03 1.025 1.02 1.015 1.01 1.005 1 0.995 0.99 0.985 65 khz 100 khz figure 16. ncp1124 v fold vs. junction temperature temperature ( c) v fold (v) ?50 125 100 ?25 0 25 50 75 1.7 1.65 1.6 1.55 1.5 1.45 65 khz 100 khz figure 17. ncp1126 v freeze vs. junction temperature temperature ( c) 125 85 25 0 ?40 0.985 0.990 0.995 1.000 1.005 1.010 1.015 v freeze (v) 65 khz 100 khz figure 18. ncp1126 v fold vs. junction temperature temperature ( c) 1.40 1.45 1.50 1.55 1.60 1.65 v fold (v) 125 85 25 0 ?40 65 khz 100 khz figure 19. NCP1129 v freeze vs. junction temperature temperature ( c) 125 100 85 25 0 ?25 ?40 0.995 1.000 1.005 1.010 1.015 v freeze (v) 65 khz 100 khz figure 20. NCP1129 v fold vs. junction temperature temperature ( c) 1.40 1.45 1.50 1.55 1.60 1.65 v fold (v) 65 khz 100 khz 125 100 85 25 0 ?25 ?40
ncp1124, ncp1126, NCP1129 http://onsemi.com 10 typical characteristics figure 21. ncp1124 f osc vs. junction temperature temperature ( c) f osc (khz) ?50 120 125 100 ?25 0 25 50 75 65 khz 100 khz figure 22. ncp1124 v cc(ovp) vs. junction temperature temperature ( c) v cc(ovp) (v) ?50 27.85 12 5 100 ?25 0 25 50 75 27.8 27.75 27.7 27.65 27.6 27.55 100 khz 65 khz 100 80 60 40 20 0 figure 23. ncp1126 f osc vs. junction temperature temperature ( c) 0 20 40 60 80 100 120 f osc (khz) 125 85 25 0 ?40 65 khz 100 khz figure 24. ncp1126 v cc(ovp) vs. junction temperature temperature ( c) v cc(ovp) (v) ?50 27.85 125 100 ?25 0 25 50 75 27.8 27.75 27.7 27.65 27.6 27.55 100 khz 65 khz figure 25. NCP1129 f osc vs. junction temperature temperature ( c) 40 50 60 70 80 90 100 110 f osc (khz) 125 100 85 25 0 ?25 ?40 65 khz 100 khz figure 26. NCP1129 v cc(ovp) vs. junction temperature temperature ( c) 125 100 85 25 0 ?25 ?40 28.15 28.20 28.25 28.30 28.35 28.40 28.45 v cc(ovp) (v) 65 khz 100 khz
ncp1124, ncp1126, NCP1129 http://onsemi.com 11 typical characteristics 780 figure 27. ncp1124 v br(dss) vs. junction temperature temperature ( c) v br(dss) (v) ?50 125 100 ?25 0 25 50 75 figure 28. ncp 1124 r ds(on) vs. junction temperature temperature ( c) r ds(on) 20 18 16 14 12 10 8 6 4 2 0 760 740 720 700 680 660 640 ?50 125 100 ?25 0 25 50 75 600 650 700 750 800 figure 29. ncp1126 v br(dss) vs. junction temperature temperature ( c) v br(dss) (v) ?50 125 100 ?25 0 25 50 75 figure 30. ncp 1126 r ds(on) vs. junction temperature temperature ( c) r ds(on) 12 10 8 6 4 2 0 ?50 125 100 ?25 0 25 50 75 600 650 700 750 800 figure 31. NCP1129 v br(dss) vs. junction temperature temperature ( c) v br(dss) (v) ?50 125 100 ?25 0 25 50 75 550 500 125 100 85 25 0 ?25 ?40 temperature ( c) r ds(on) figure 32. ncp 1129 r ds(on) vs. junction temperature 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
ncp1124, ncp1126, NCP1129 http://onsemi.com 12 typical characteristics ?v ds , drain?to?source voltage (v) c, capacitance (pf) 350 0 250 50 200 100 150 i d , drain current (a) v ds , drain?to?source voltage (v) 2 030 27 36912 24 15 18 21 1.5 1 0.5 0 v gs = 6 ? 8.5 v v gs = 5.5 v v gs = 5 v v gs = 4.5 v v gs = 4 v figure 33. ncp1124 ? drain current vs. drain?to?source voltage 0 figure 34. ncp1124 ? capacitance variation 300 250 200 150 100 50 c oss v gs = 0 v t j = 25 c f = 1 mhz figure 35. ncp1126 ? drain current vs. drain?to?source voltage v ds , drain?to?source voltage (v) i d , drain current (a) 3.5 030 27 36912 24 3 2.5 2 1.5 1 0.5 0 15 18 21 v gs = 6 ? 8.5 v v gs = 5.5 v v gs = 5 v v gs = 4.5 v v gs = 4 v figure 36. ncp1126 ? capacitance variation ?v ds , drain?to?source voltage (v) c, capacitance (pf) 600 0 250 50 200 100 150 i d , drain current (a) 10 9 8 7 6 5 4 3 2 1 0 030 27 36912 24 15 18 21 v ds , drain?to?source voltage (v) figure 37. NCP1129 ? drain current vs. drain?to?source voltage ?v ds , drain?to?source voltage (v) c, capacitance (pf) 0 250 50 200 100 150 figure 38. NCP1129 ? capacitance variation v gs = 6 ? 8.5 v v gs = 5.5 v v gs = 5 v v gs = 4.5 v v gs = 4 v 500 400 300 200 100 0 c oss v gs = 0 v t j = 25 c f = 1 mhz 1600 1200 1000 800 600 400 200 0 v gs = 0 v t j = 25 c f = 1 mhz c oss
ncp1124, ncp1126, NCP1129 http://onsemi.com 13 application information introduction the ncp112x family integrates a high?performance current?mode controller with a 650 v mosfet, which considerably simplifies the design of a compact and reliable switch mode power supply (smps). this component represents the ideal candidate where low part?count and cost effectiveness are the key parameters. the ncp112x brings most necessary functions needed in today?s modern power supply designs, with several enhancements such as v cc ovp, adjustable slope compensation, frequency jittering, frequency foldback, skip cycle, etc. ? current?mode operation with adjustable internal ramp compensation: sub?harmonic oscillations in peak current mode control can be eliminated by the adjustable internal ramp compensation when the duty ratio is larger than 0.5. ? frequency foldback capability: when the load current drops, the controller responds by reducing the primary peak current. when the peak current reaches the skip peak current level, the ncp112x enter skip operation to reduce the power consumption. ? internal soft?start: a soft?start precludes the main power switch from being stressed upon start?up. in this switcher, the soft?start is internally fixed to 4 ms. soft?start is activated when a new startup sequence occurs or during an auto?recovery hiccup. ? latched ovp on v cc : when the v cc exceeds 28 v typical, the drive signal is disabled and the part latches off. when the user cycles the v cc down, the circuit is reset and the part enters a new start up sequence. ? short?cir cuit protection: short?circuit and especially over?load protections are difficult to implement when a strong leakage inductance between the auxiliary and the power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). every time the internal 0.8 v maximum peak current limit is activated, an error flag is asserted and an internal timer starts. when the fault is validated, the switcher will either be latched or enter the auto?recovery mode. as soon as the fault disappears, the smps resumes operation. ? emi jittering: an internal low?frequency 240 hz modulation signal varies the pace at which the oscillator frequency is modulated. this helps spread out the energy in a conducted noise analysis. to improve the emi signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). start?up sequence the ncp112x need an external startup circuit to provide the initial energy to the switcher. as is shown in figure 39, the startup circuit consists of r start and v cc capacitor c cc , connected to the main input, i.e. half?wave connection. the auxiliary winding will take over the rc circuit after the output voltage is built up. d auxiliary winding main input v cc figure 39. startup circuit for ncp112x (half?wave connection) d 2 d 4 d 1 d 3 c bulk c cc r start the startup process can be well explained by figure 40. at power on, when the v cc capacitor is fully discharged, the switcher current consumption is zero and does not deliver any driving pulses. the v cc capacitor c cc is going to be charged by the main input via r start . as v cc increases, the switcher consumed current remains below a guaranteed limit until the voltage on the capacitor reaches v cc(on) , at which point the switcher starts to deliver pulses to the power mosfet. the switcher current consumption suddenly increases, and the capacitor depletes since it is the only energy reservoir. its voltage falls until the auxiliary winding takes over and supply the v cc pin. drive time margin figure 40. startup process for ncp112x v cc(off) v cc(on ) v cc t 1 : 5?20 ms the start?up current of the switcher is extremely low, below 15 a. the start?up resistor can be connected to the bulk capacitor or directly the mains input voltage for further power dissipation reduction. the switcher begins switching when v cc reaches v cc(on) , typically 17 v for ncp1126/9. from figure 41, it can be seen that the startup resistor r start and v cc capacitor are about to be determined.
ncp1124, ncp1126, NCP1129 http://onsemi.com 14 v cc capacitor the supply capacitor, c cc , provides power to the switcher during power up. the capacitor must be large enough such that a v cc voltage greater than v cc(off) is maintained while the auxiliary supply voltage is building up. otherwise, v cc will collapse and the switcher will turn off. assuming this time t 1 is equal to 10 ms, equation 1 is used to calculate the required v cc capacitor. c cc i cc t 1 v cc(on) v cc(off) (eq. 1) startup resistor r start in order to determine the startup resistor, the v cc capacitor charging current is calculated first to ensure that the charging time for the v cc capacitor from 0 v to its operating voltage meets the startup time requirement. equation 2 gives the first constraints for the r start selection. i charge v cc(on) c cc t startup (eq. 2) for ncp1126/9, during startup process, from 0 to t 1 , the current that flow inside the switcher is i cc1 , therefore the total charging current from the main input is going to be i c = i charge + i cc1 . consider the half?wave connection start?up network to the mains as is shown in figure 41, the average current flowing into this start?up resistor will be the smallest when v cc reaches the v cc(on) of the switcher: i c,min v ac,rms 2 v cc(on) r start?up (eq. 3) which gives the minimum value for the r startup , r start?up v ac,rms 2 v cc(on) i c,min (eq. 4) note that this calculation is purely theoretical, considering a constant charging current. in reality , the take over time can be shorter (or longer!) and it can lead to a reduction of the v cc capacitor. this brings a decrease in the char ging current and an increase of the start?up resistor, for the benefit of standby power. the dissipated power at high line amounts to: p diss v 2 ac,peak 4r start (eq. 5) the above derivation is based on the case when the power supply is not at light load. v cc capacitor selection should ensure that does not disappear in no?load conditions. in light load condition, the skip?cycle can be so deep that refreshing pulses are likely to be widely spaced, inducing a large ripple on the v cc capacitor. if this ripple is too large, chances exist to hit the v cc(off) and reset the switcher into a new start?up sequence. a solution is to grow this capacitor but it will obviously be detrimental to the start?up time. the option offered in figure 41 elegantly solves this potential issue by adding an extra capacitor c cc,aux on the auxiliary winding. however, this component is separated from the v cc pin by a simple diode. you therefore have the ability to grow this capacitor as you need to ensure the self?supply of the switcher without affecting the start?up time and standby power. auxiliary winding main input vcc figure 41. startup circuit for ncp112x (half?wave connection), considering light load condition d 5 c cc d 4 r start c cc,aux c bulk d 4 d 2 d 3 d 1 frequency foldback the reduction of no?load standby power associated with the need for improving the efficiency, requires a change in the traditional type of fixed?frequency operation. ncp112x implement a switching frequency foldback function when the feedback voltage is below v fb(fold) . at this point, the oscillator turns into a voltage?controlled oscillator and reduces its switching frequency. the peak current setpoint follows the feedback pin until its level reaches v fb(freeze) . below this value, the peak current freezes to v fb(freeze) / 4. the operating frequency is down to f trans when the feedback voltage reaches v fb(fold,end) . below this point, if the output power continues to decrease, the part enters skip mode for the best noise?free performance in no?load conditions. figure 6 depicts the adopted scheme for the part. over?voltage protection the latched?state of the ncp112x is maintained via an internal thyristor (scr). when the voltage on pin 1 exceeds the latch voltage for four consecutive clock cycles, the scr is fired and immediately stops the output pulses. the same scr is fired when an ovp is sensed on the v cc pin. when this happens, all pulses are stopped and v cc is discharged to a fix level of 7 v typically: the circuit is latched and the converter no longer delivers pulses. to maintain the latched?state, a permanent current must be injected in the part. if too low of a current, the part de?latches and the converter resumes operation. this current is characterized to 32 a as a minimum but we recommend including a design margin and select a value around 60 a. the test is to latch the part and reduce the input voltage until it de?latches. if you de?latch at v in = 70 v rms for a minimum voltage of 85 v rms , you are fine.
ncp1124, ncp1126, NCP1129 http://onsemi.com 15 min max f trans min max 3.2 v 3.2 v frequency figure 42. frequency foldback architecture v fb v cs v ilim v cs(fold) v cs(freeze) v fb(freeze) v fb(fold) v fb v fb(fold) v fb(fold,end) f osc f sw if it precociously recovers, you will have to increase the start?up current, unfortunately to the detriment of standby power. the most sensitive configuration is actually that of the half?wave connection proposed in figure 39. as the current disappears 5 ms for a 10 ms period (50 hz input source), the latch can potentially open at low line. if you really reduce the start?up current for a low standby power design, you must ensure enough current in the scr in case of a faulty event. an alternate connection to the above is shown in figure 43: figure 43. the full?wave connection ensures latch current continuity as well as a x2?discharge path in this case, the current is no longer made of 5 ms ?holes? and the part can be maintained at a low input voltage. experiments show that these 2?m resistor help to maintain the latch down to less than 50 v rms, giving an excellent design margin. standby power with this approach was also improved compared to figure 39 solution. please note that these resistors also ensure the discharge of the x2?capacitor up to a 0.47 f type. the de?latch of the scr occurs when a) the injected current in the v cc pin falls below the minimum stated in the data?sheet (32 a at room temp) or when the part senses a brown?out recovery. auto?recovery short?circuit protection in case of output short?circuit or severe overload situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than t ovld , the driving pulses are stopped and v cc falls down as the auxiliary pulses are missing. when it hits v cc(off) , the switcher consumption is down to a few a and the v cc slowly builds up again by the startup network r start , c cc . when v cc reaches v cc(on) , the switcher purposely ignores the re?start and waits for another v cc cycle: this is the so?called double hiccup. illustration of such principle appears in figure 13. please note that soft?start is activated upon re?start attempt. drive time figure 44. auto?recovery double hiccup sequence v cc v cc(off) v cc(on)
ncp1124, ncp1126, NCP1129 http://onsemi.com 16 adjustable ramp compensation the ncp112x also include an internal ramp compensation signal. this is the buffered oscillator clock delivered during the on time only. its amplitude v ramp is around 2.5 v at maximum duty?cycle. ramp compensation is a well?known method used to eliminate the sub?harmonic oscillations in ccm peak current mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty?ratio greater than 50%. to lower the current loop gain, one usually mixes between 50% and 100% of the inductor downslope with the current?sense signal. figure 45 depicts how internally the ramp is generated. note that the ramp signal will be disconnected from the cs pin, during the off?time. figure 45. internal adjustable ramp compensation architecture in the ncp112x switchers, the oscillator ramp exhibits a v ramp 2.5 v swing reached at its maximum duty?ratio. if the clock operates at a 65?khz frequency, then the slope of the ramp is equal to: s ramp v ramp d max t sw (eq. 6) the off?time primary current slope s p is thus given by equation 7: s p v out v f n p n s l p (eq. 7) given a sense resistor r sense the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense (eq. 8) the slope of compensation ramp is chosen to be the same as the downslope of the sensing ramp for better transient response. the internal resistor connected to the compensation ramp is 20 k . the series compensation resistor value is therefore: r comp r ramp s sense s ramp (eq. 9) a resistor of the above value will then be inserted from the sense resistor to the current sense pin. a100 pf capacitor is recommended to be added to the current sense pin to the switcher ground for improved noise immunity with the current sensing components located very close to the switcher.
ncp1124, ncp1126, NCP1129 http://onsemi.com 17 figure 46. pin connections 1 3 2 5 6 8 4 (top view) vcc fb cs source gnd drain drain ordering information device package shipping ncp1124ap65g pdip?7 (pb?free) 50 units / rail ncp1124bp65g pdip?7 (pb?free) 50 units / rail ncp1124ap100g pdip?7 (pb?free) 50 units / rail ncp1124bp100g pdip?7 (pb?free) 50 units / rail ncp1126ap65g pdip?7 (pb?free) 50 units / rail ncp1126bp65g pdip?7 (pb?free) 50 units / rail ncp1126ap100g pdip?7 (pb?free) 50 units / rail ncp1126bp100g pdip?7 (pb?free) 50 units / rail NCP1129ap65g pdip?7 (pb?free) 50 units / rail NCP1129bp65g pdip?7 (pb?free) 50 units / rail NCP1129ap100g pdip?7 (pb?free) 50 units / rail NCP1129bp100g pdip?7 (pb?free) 50 units / rail
ncp1124, ncp1126, NCP1129 http://onsemi.com 18 package dimensions pdip?7 (pdip?8 less pin 7) case 626b issue c 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension e3 is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 m 8x c d1 b h note 5 e e/2 a2 note 3 m b m note 6 m dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1126/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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